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19-2646; Rev 0; 10/02
50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP
General Description
The MAX4747-MAX4750 low-voltage, quad single-pole single-throw (SPST)/dual single-pole/double-throw (SPDT) analog switches operate from a single +2V to +11V supply and handle Rail-to-Rail(R) analog signals. These switches exhibit low leakage current (0.1nA) and consume less than 0.5nW (typ) of quiescent power, making them ideal for battery-powered applications. When powered from a +3V supply, these switches feature 50 (max) on-resistance (RON), with 3.5 (max) matching between channels and 9 (max) flatness over the specified signal range. The MAX4747 has four normally open (NO) switches, the MAX4748 has four normally closed (NC) switches, and the MAX4749 has two NO and two NC switches. The MAX4750 has two SPDT switches. These switches are available in 14-pin TSSOP and 16-bump chip-scale packages (UCSPTM). This tiny chip-scale package occupies a 2mm 2mm area and significantly reduces the required PC board area.
Features
o 2mm 2mm UCSP o Guaranteed On-Resistance (RON) 25 (max) at +5V 50 (max) at +3V o On-Resistance Matching 3 (max) at +5V 3.5 (max) at +3V o Guaranteed <0.1nA Leakage Current at TA = +25C o Single-Supply Operation from +2.0V to +11V o TTL/CMOS-Logic Compatible o -84dB Crosstalk (1MHz) o -72dB Off-Isolation (1MHz) o Low Power Consumption: 0.5nW (typ) o Rail-to-Rail Signal Handling
MAX4747-MAX4750
Applications
Battery-Powered Systems Audio/Video-Signal Routing Low-Voltage Data-Acquisition Systems Cell Phones Communications Circuits Glucose Meters PDAs
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. UCSP is a trademark of Maxim Integrated Products, Inc. Pin Configurations/Truth Tables continued at end of data sheet.
PART MAX4747EUD MAX4747EBE-T*
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-/BUMPPACKAGE 14 TSSOP 16 UCSP-16 TOP MARK -- 4747
Note: Requires special solder temperature profile described in the Absolute Maximum Ratings section. Ordering Information continued at end of data sheet. *UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and environment. See the UCSP Reliability section for more information.
Pin Configurations/Truth Tables
TOP VIEW (BUMPS SIDE DOWN)
1 2 3 4
TOP VIEW MAX4747
NO1 1 COM1 2 NO2 3 COM2 4 IN2 5 IN3 6 GND 7 14 V+ 13 IN1 12 IN4 11 NO4 10 COM4 9 COM3 INPUT LOW HIGH
COM1 A SWITCH STATE OFF ON C IN4 8 NO3 D NO1 B IN1
NO2
COM2
IN2
V+
IN3
GND
NO3
NO4
COM4
COM3
TSSOP UCSP
________________________________________________________________ Maxim Integrated Products
1
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747-MAX4750
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND) V+ ...........................................................................-0.3V to +12V IN_, COM_, NO_, NC_ (Note 1)....................-0.3V to (V+ + 0.3V) Continuous Current (any pin) ...........................................10mA Peak Current (any pin, pulsed at 1ms, 10% duty cycle) ...20mA Continuous Power Dissipation (TA = +70C) 14-Pin TSSOP (derate 6.3mW/C above +70C) .........500mW 16-Bump UCSP (derate 8.3mW/C above +70C) ......659mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Bump Temperature (soldering, Note 2) Infrared (15s) ...............................................................+220C Vapor Phase (60s) .......................................................+215C Lead Temperature (soldering, 10s) .................................+300C
Note 1: Signals on IN_, NO_, NC_, or COM_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--Single +3V Supply
(V+ = +3V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25C.) (Notes 3, 4)
PARAMETER ANALOG SWITCH Analog Signal Range VCOM_, VNO_, VNC_ +25C On-Resistance RON V+ = +2.7V, ICOM_ = 5mA, VNO_ or VNC_ = +1.5V V+ = +2.7V, ICOM_ = 5mA, VNO_ or VNC_ = +1.5V V+ = +2.7V, ICOM_ = 5mA, VNO_ or VNC_ = +1V, +1.5V, +2V V+ = +3.6V, VCOM_ = +0.3V, +3V, VNO_ or VNC_ = +3V, +0.3V TMIN to TMAX +25C RON TMIN to TMAX +25C On-Resistance Flatness (Note 7) RFLAT(ON) TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX -0.1 -2 -0.1 -2 -0.2 -4 2.7 0.2 0 17 V+ 50 60 3.5 4.5 9 11 +0.1 +2 +0.1 +2 +0.2 nA +4 nA nA V SYMBOL CONDITIONS TA MIN TYP MAX UNITS
On-Resistance Matching Between Channels (Notes 5, 6)
NO_ or NC_ Off-Leakage Current (Note 8) COM_ Off-Leakage Current (Note 8)
INO_(OFF), INC_(OFF)
V+ = +3.6V, ICOM_(OFF) VCOM_ = +0.3V, +3V, VNO_ or VNC_ = +3V, +0.3V V+ = +3.6V, VCOM_ = +0.3V, +3.0V, VNO_ or VNC_ = +0.3V, +3V, or floating
COM_ On-Leakage Current (Note 8)
ICOM_(ON)
2
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS--Single +3V Supply (continued)
(V+ = +3V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25C.) (Notes 3, 4)
PARAMETER DYNAMIC +25C Turn-On Time tON VNO_ or VNC_ = +1.5V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +1.5V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +1.5V, RL = 300, CL = 35pF, Figure 3 VGEN = 0V, RGEN = 0, CL = 1.0nF, Figure 4 Signal = 0dBm, 50 in and out f = 1MHz, VNO_ = 1VRMS, RL = 50, CL = 5pF, Figure 5 f = 1MHz, VNO_ = 1VRMS, RL = 50, CL = 5pF, Figure 6 f = 1MHz, Figure 7 TMIN to TMAX +25C Turn-Off Time tOFF TMIN to TMAX +25C tBBM TMIN to TMAX +25C +25C +25C +25C +25C +25C +25C 2 0.8 VIN_ = 0V or V+ -1 2 V+ = +5.5V, VIN_ = 0V or V+, all switches on or off 0.0001 +0.005 +1 11 1 1 7 250 -72 84 20 20 40 33 ns 24 57 150 170 60 70 ns ns SYMBOL CONDITIONS TA MIN TYP MAX UNITS
MAX4747-MAX4750
Break-Before-Make (MAX4749/MAX4750 Only) (Note 8) Charge Injection On-Channel -3dB Bandwidth Off-Isolation (Note 9) Crosstalk (Note 10) NO_ or NC_ Off-Capacitance COM_ Off-Capacitance COM_ On-Capacitance LOGIC INPUT Input Logic High Input Logic Low Input Leakage Current POWER SUPPLY Power-Supply Range Positive Supply Current
Q BW VISO VCT COFF
pC MHz dB dB pF pF pF V V A V A
CCOM_(OFF) f = 1MHz, Figure 7 CCOM_(ON) f = 1MHz, Figure 7 VIH VIL IIN V+ I+
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747-MAX4750
ELECTRICAL CHARACTERISTICS--Single +5V Supply
(V+ = +5V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25C.) (Notes 3, 4)
PARAMETER ANALOG SWITCH Analog Signal Range VCOM_, VNO_, VNC_ RON V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +3.0V V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +3.0V V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +1V, +2V, +3V V+ = +5.5V, VCOM_ = +1V, +4.5V, VNO_ or VNC_ = +4.5V, +1V +25C TMIN to TMAX +25C RON TMIN to TMAX +25C On-Resistance Flatness (Notes 7) RFLAT(ON) TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C +25C +25C 1 9 250 -72 14 ns 19 -0.1 -2 -0.1 -2 -0.2 -4 2.2 0.1 0 8.2 V+ 25 30 3 4 5 7 +0.1 +2 +0.1 +2 +0.2 nA +4 nA nA V SYMBOL CONDITIONS TA MIN TYP MAX UNITS
On-Resistance
On-Resistance Matching Between Channels (Notes 5, 6)
NO_ or NC_ Off-Leakage Current (Note 8)
INO_(OFF), INC_(OFF)
COM_ Off-Leakage Current (Note 8)
V+ = +5.5V, ICOM_(OFF) VCOM_ = +1V, +4.5V, VNO_ or VNC_ = +4.5V, +1V V+ = +5.5V, VCOM_ = +1V, +4.5V, VNO_ or VNC_ = +1V, +4.5V, or floating
COM_ On-Leakage Current (Note 8) DYNAMIC Turn-On Time
ICOM_(ON)
tON
VNO_ or VNC_ = +3.0V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +3.0V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +3.0V, RL = 300, CL = 35pF, Figure 3 VGEN = 0V, RGEN = 0, CL = 1.0nF, Figure 4 Signal = 0dBm, 50 in and out f = 1MHz, VNO_= 1VRMS, RL = 50, CL = 5pF, Figure 5
36
85 95 45 55 ns ns
Turn-Off Time
tOFF
Break-Before-Make (MAX4749/MAX4750 Only) (Note 8) Charge Injection On-Channel -3dB Bandwidth Off-Isolation (Note 9)
tBBM
Q BW VISO
pC MHz dB
4
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS--Single +5V Supply (continued)
(V+ = +5V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25C.) (Notes 3, 4)
PARAMETER Crosstalk (Note 10) NO_ or NC_ Off-Capacitance COM_ Off-Capacitance COM_ On-Capacitance LOGIC INPUT Input Logic High Input Logic Low Input Leakage Current POWER SUPPLY Power-Supply Range Positive Supply Current V+ I+ V+ = +5.5V, VIN_ = 0V or V+, all switches on or off 2 0.0001 11 1 V A VIH VIL IIN VIN_ = 0V or V+ -1 +0.005 2 0.8 +1 V V A SYMBOL VCT COFF CONDITIONS f = 1MHz, VNO_ = 1VRMS, RL = 50, CL = 5pF, Figure 6 f = 1MHz, Figure 7 TA +25C +25C +25C +25C MIN TYP -84 20 20 40 MAX UNITS dB pF pF pF
MAX4747-MAX4750
CCOM_(OFF) f = 1MHz, Figure 7 CCOM_(ON) f = 1MHz, Figure 7
The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 4: UCSP parts are 100% tested at +25C only, and are guaranteed by design over temperature. TSSOP parts are 100% tested at +85C and guaranteed by design over temperature. Note 5: RON = RON(MAX) - RON(MIN). Note 6: UCSP on-resistance matching between channels is guaranteed by design. Note 7: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. Note 8: Guaranteed by design. Note 9: Off-isolation = 20 log10 (VNO_/VCOM_), VNO_ = output, VCOM_ = input to off switch. Note 10: Between any two switches. Note 3:
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
ON-RESISTANCE vs. VCOM
MAX4747-50-toc01
ON-RESISTANCE vs. VCOM
MAX4747-50-toc02
ON-RESISTANCE vs. VCOM
V+ = 3V
MAX4747-50-toc03
50
16
30 25 20 RON () 15 10 TA = +85C TA = +25C
V+ = 5V TA = +85C TA = +25C
40 V+ = 2V RON () 30
12 RON ()
8
20 V+ = 3V 10 V+ = 5V V+ = 11V 0 0 2 4 6 VCOM (V) 8 10 12 0 1 2 3 4 5 VCOM (V) 4 TA = -40C 5 0 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0 TA = -40C
0
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747-MAX4750
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
ON-RESISTANCE vs. VCOM
MAX4747-50-toc04
SUPPLY CURRENT vs. TEMPERATURE
MAX4747-50-toc05
LEAKAGE vs. TEMPERATURE
V+ = 5V, VCOM = 4.5V, NO_ or NC_ = FLOATING LEAKAGE CURRENT (pA) 10 ON 1 OFF
MAX4747-50-toc06
30 25 20 RON () 15 10 TA = -40C 5 0 0 0.5 1.0 TA = +85C
V+ = 2.5V TA = +25C
10,000
100
1000 SUPPLY CURRENT (pA)
V+ = 3V, 5V
100
10
1
0.1
0.1 1.5 2.0 2.5 -40 -15 10 35 60 85 VCOM (V) TEMPERATURE (C)
0.01 -40 -15 10 35 60 85 TEMPERATURE (C)
IN LOGIC THRESHOLD vs. SUPPLY VOLTAGE
MAX4747-50-toc07
FREQUENCY RESPONSE
MAX4747-50-toc08
3.5 LOGIC THRESHOLD (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8
VNO_ = V+
-10 GAIN (dB)/PHASE (DEGREES) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0.01 0.1 1 10 100 CROSSTALK OFFISOLATION PHASE LOSS
50 40 30 20 10 0 0 2 4 6
V+ = 11V
CHARGE (pC)
V+ = 5V
V+ = 3V 8 10 12
10
12
1000
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
VCOM (V)
TURN-ON/OFF TIME vs. TEMPERATURE
MAX4747-50-toc10
TURN-ON/OFF TIME vs. SUPPLY VOLTAGE
MAX4747-50-toc11
TOTAL HARMONIC DISTORTION vs. FREQUENCY
SOURCE AND LOAD = 600 VCOM = 2VP-P V+ = 3V
MAX4747-50 toc12
80 70 TURN-ON/OFF TIME (ns) 60 50 40 30 20 10 0 -40 -15 10 35 60 tOFF, V+ = 3V tOFF, V+ = 5V tON, V+ = 3V tON, V+ = 5V
120 VNO = V+/2 100 TURN-ON/OFF TIME (ns) 80 60 tOFF 40 20 0 tON
1
0.1 THD (%)
V+ = 5V 0.01
0.001 0 2 4 6 8 10 12 0.01 0.1 1 FREQUENCY (kHz) 10 100 SUPPLY VOLTAGE (V)
85
TEMPERATURE (C)
6
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MAX4747-50-toc09
4.0
0
CHARGE INJECTION vs. VCOM
60
50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP
Pin Description--TSSOP
PIN MAX4747 1, 3, 8, 11 -- -- -- -- -- 2, 4, 9, 10 -- 13, 5, 6, 12 -- 7 14 -- MAX4748 -- 1, 3, 8, 11 -- -- -- -- 2, 4, 9, 10 -- 13, 5, 6, 12 -- 7 14 -- MAX4749 -- -- 1, 8 -- -- 3, 11 2, 4, 9, 10 -- 13, 5, 6, 12 -- 7 14 -- MAX4750 -- -- -- 1, 8 4, 11 -- -- 2, 9 -- 13, 6 7 14 3, 5, 10, 12 NAME NO1-NO4 NC1-NC4 NO1, NO3 NO1, NO2 NC1, NC2 NC2, NC4 COM1-COM4 COM1, COM2 IN1-IN4 IN1, IN2 GND V+ N.C. FUNCTION Analog-Switch Normally Open Terminals Analog-Switch Normally Closed Terminals Analog-Switch Normally Open Terminals Analog-Switch Normally Open Terminals Analog-Switch Normally Closed Terminals Analog-Switch Normally Closed Terminals Analog-Switch Common Terminal Analog-Switch Common Terminal Logic-Control Digital Input Logic-Control Digital Input Ground. Connect to digital ground. Positive Analog and Digital Supply Voltage Input. Internally connected to substrate. No Connection. Not internally connected.
MAX4747-MAX4750
Pin Description--UCSP
PIN MAX4747 B1, A2, C4, D2 -- -- -- -- -- A1, A3, D4, D3 -- C1, A4, B4, D1 -- C3 B2 -- MAX4748 -- B1, A2, C4, D2 -- -- -- -- A1, A3, D4, D3 -- C1, A4, B4, D1 -- C3 B2 -- MAX4749 -- -- B1, C4 -- -- A2, D2 A1, A3, D4, D3 -- C1, A4, B4, D1 -- C3 B2 -- MAX4750 -- -- -- B1, C4 A3, D2 -- -- A1, D4 -- C1, B4 C3 B2 A2, A4, D1, D3 NAME NO1-NO4 NC1-NC4 NO1, NO3 NO1, NO2 NC1, NC2 NC2, NC4 COM1-COM4 COM1, COM2 IN1-IN4 IN1, IN2 GND V+ N.C. FUNCTION Analog-Switch Normally Open Terminals Analog-Switch Normally Closed Terminals Analog-Switch Normally Open Terminals Analog-Switch Normally Open Terminals Analog-Switch Normally Closed Terminals Analog-Switch Normally Closed Terminals Analog-Switch Common Terminal Analog-Switch Common Terminal Logic-Control Digital Input Logic-Control Digital Input Ground. Connect to digital ground. Positive Analog and Digital Supply Voltage Input. Internally connected to substrate. No Connection. Not internally connected.
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747-MAX4750
Applications Information
Operating Considerations for High-Voltage Supply
The MAX4747-MAX4750 operate to +11V with some precautions. The absolute maximum rating for V+ is +12V (referenced to GND). When operating near this region, bypass V+ with a minimum 0.1F capacitor to ground as close to the IC as possible.
EXTERNAL BLOCKING DIODE V+
Test Circuits/Timing Diagrams
V+ D1
MAX4747- MAX4750
*
NO_
*
COM_
Logic Levels
The MAX4747-MAX4750 are TTL compatible when powered from a single +3V supply. When powered from other supply voltages, the logic inputs should be driven rail-to-rail. For example, with a +11V supply, IN_ should be driven low to 0V and high to 11V. With a +3.3V supply, IN_ should be driven low to 0V and high to 3.3V. Driving IN_ rail-to-rail minimizes power consumption.
*
GND EXTERNAL BLOCKING DIODE GND D2
*
*INTERNAL PROTECTION DIODES
Analog Signal Levels
Analog signals that range over the entire supply voltage (GND to V+) pass with very little change in RON (see the Typical Operating Characteristics). The bidirectional switches allow NO_, NC_, and COM_ connections to be used as either inputs or outputs.
Figure 1. Overvoltage Protection Using External Blocking Diodes
Power-Supply Sequencing and Overvoltage Protection
CAUTION: Do not exceed the absolute maximum ratings. Stresses beyond the listed ratings can cause permanent damage to the devices. Proper power-supply sequencing is recommended for all CMOS devices. Always apply V+ before applying analog signals, especially if the analog signal is not current limited. If this sequencing is not possible, and if the analog inputs are not current limited to <20mA, add small-signal diode D1 as shown in Figure 1. If the analog signal can dip below GND, add D2. Adding protection diodes reduces the analog signal range to a diode drop (about 0.7V) below V+ (for D1), and to a diode drop above ground (for D2). Leakage is unaffected by adding the diodes. On-resistance increases slightly at low supply voltages. Maximum supply voltage (V+) must not exceed +11V. Adding protection diodes causes the logic thresholds to be shifted relative to the power-supply rails. The most significant shift occurs when using low supply voltages (+5V or less). With a +5V supply, TTL compatibility is not guaranteed when protection diodes are added. Driving IN_ and IN_ all the way to the supply rails (i.e., to a diode drop higher than the V+ pin, or to a diode drop lower than the GND pin) is always acceptable.
Protection diodes D1 and D2 also protect against some overvoltage situations. Using the circuit in Figure 1, no damage results if the supply voltage is below the absolute maximum rating (+12V) and if a fault voltage up to the absolute maximum rating (V+ + 0.3V) is applied to an analog signal terminal.
UCSP Considerations
For general UCSP information and PC layout considerations, refer to Maxim Application Note Wafer-Level Chip-Scale Packages.
UCSP Reliability
The chip-scale package (UCSP) represents a unique package that greatly reduces board space compared to other packages. UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering a UCSP. Performance through operation life test and moisture resistance is equal to conventional package technology as the waferfabrication process primarily determines it. However, this form factor may not perform equally to a packaged product through traditional mechanical reliability tests. Mechanical stress performance is a greater consideration for a UCSP. UCSP solder joint contact integrity must be considered since the package is attached through direct solder contact to the user's PC board. Testing done to characterize the UCSP reliability performance shows that it is capable of performing reliably through environmental stresses. Results of environmental stress test and additional usage data and recommendations are detailed in the UCSP application note, which can be found on Maxim's website at www.maxim-ic.com.
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747-MAX4750
Test Circuits/Timing Diagrams (continued)
MAX4747- MAX4750
NO_ OR NC_ V+ V+ COM_ RL 300 IN_ LOGIC INPUT GND SWITCH OUTPUT 0 tON LOGIC INPUT VOUT CL 35pF VOUT 0.9 x VOUT tOFF VIH 50% VIL
tr < 5ns tf < 5ns
VN_
0.9 x VOUT
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL VOUT = VN_ ( RL + RON )
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching Time
MAX4749
NO_ NC_ IN_ LOGIC INPUT IN_ GND
V+ V+ VOUT1 VOUT2 RL2 300 CL2 35pF CL1 35pF LOGIC INPUT
VIH 50% VIL
tr < 5ns tf < 5ns
VN_
COM_ COM_ RL1 300
SWITCH OUTPUT 1 (VOUT1) SWITCH OUTPUT 2 (VOUT2)
0.9 x V0UT1 0
0.9 x VOUT2 0 tBBM tBBM
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Interval
V+
MAX4747- MAX4750
RGEN NC_ OR NO_ GND IN_
VOUT VOUT VOUT IN OFF ON OFF
V+ COM CL 1nF
V GEN
VILTO VIH
IN
OFF
ON Q = (V OUT )(C L )
OFF
IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection _______________________________________________________________________________________ 9
50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747-MAX4750
Test Circuits/Timing Diagrams (continued)
10nF SIGNAL GENERATOR 0dBm V+ 10nF V+
MAX4747- MAX4750
MAX4747- MAX4750
NO_/NC_ IN_ 50
V+ COM_ VIL OR VIH
SIGNAL GENERATOR 0dBm
V+ COM_ IN_
IN_ ANALYZER RL NC_ OR NO_ GND 10nF
0 OR 2.4V
0 OR 2.4V N.C.
ANALYZER RL
NO_/NC_ GND 10nF
COM_
VDUAL SUPPLIES USED TO ACCOMMODATE GROUND-REFERENCED INSTRUMENTS.
VDUAL SUPPLIES USED TO ACCOMMODATE GROUND-REFERENCED INSTRUMENTS.
Figure 5. Off-Isolation/On-Channel Bandwidth
Figure 6. Crosstalk
Ordering Information (continued)
PART
10nF V+
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
PIN-/BUMPPACKAGE 14 TSSOP 16 UCSP-16 14 TSSOP 16 UCSP-16 14 TSSOP 16 UCSP-16
TOP MARK -- 4748 -- 4749 -- 4750
MAX4747- MAX4750
MAX4748EUD MAX4748EBE-T* MAX4749EUD MAX4749EBE-T* MAX4750EUD
V+ COM_
CAPACITANCE METER f = 1MHz
IN_ NC_ OR NO_ GND
VIL OR VIH
MAX4750EBE-T*
Note: Requires special solder temperature profile described in the Absolute Maximum Ratings section. *UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and environment. See the UCSP Reliability section for more information.
Figure 7. Channel Off/On-Capacitance
Chip Information
TRANSISTOR COUNT: 130 PROCESS: CMOS
10
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50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP
Pin Configurations/Truth Tables (continued)
TOP VIEW MAX4748
COM1 NC1 1 COM1 2 NC2 3 COM2 4 IN2 5 IN3 6 GND 7 14 V+ 13 IN1 12 IN4 11 NC4 10 COM4 9 COM3 8 NC3 D IN4 NC4 COM4 COM3 INPUT LOW HIGH SWITCH STATE ON OFF IN1 C GND NC3 B A NC1 V+ IN3 NC2 COM2 IN2
MAX4747-MAX4750
TOP VIEW (BUMPS SIDE DOWN)
1
2
3
4
TSSOP UCSP TOP VIEW MAX4749
NO1 1 COM1 2 NC2 3 COM2 4 IN2 5 IN3 6 GND 7 14 V+ 13 IN1 12 IN4 11 NC4 10 COM4 9 COM3 8 NO3 D INPUT LOW HIGH NO1, NO3 OFF ON NC2, NC4 ON OFF B IN1 C IN4 NC4 COM4 COM3 GND NO3 A NO1 V+ IN3
TOP VIEW (BUMPS SIDE DOWN)
1
2
3
4
COM1
NC2
COM2
IN2
TSSOP UCSP TOP VIEW MAX4750
NO1 1 COM1 2 N.C. 3 NC1 4 N.C. 5 IN2 6 GND 7 14 V+ 13 IN1 12 N.C. 11 NC2 10 N.C. 9 COM2 8 NO2 D INPUT LOW HIGH NO1, NO2 OFF ON NC1, NC2 ON OFF B IN1 C N.C. NC2 N.C. COM2 GND NO2 A NO1 V+ IN2
TOP VIEW (BUMPS SIDE DOWN)
1
2
3
4
COM1
N.C.
NC1
N.C.
TSSOP UCSP
______________________________________________________________________________________
11
50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747-MAX4750
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12
______________________________________________________________________________________
TSSOP4.40mm.EPS
50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
16L,UCSP.EPS
MAX4747-MAX4750
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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